Embodiments relate to a semiconductor device and a method for manufacturing the same.
A metal interconnection of a semiconductor device may be formed by using a metallic thin film including, for example, aluminum (Al) or copper (Cu), etc. The metal interconnection may connect circuits formed in a semiconductor substrate through electric connection and pad connection between semiconductor devices.
To form the metal interconnection, a contact hole may be formed by selectively etching an insulating layer. A device electrode may be connected with a pad, which may be insulated from the device electrode by an insulating layer including an oxide layer, through a contact hole that may be formed by selectively etching the insulating layer. A metal plug including a barrier metal or tungsten may be used to fill in the contact hole. In addition, a metal thin film may be formed on the resultant structure. The metal thin film may then be patterned, thereby forming the metal interconnection that connects the device electrode with the pad.
A photolithography process may be commonly used to form a pattern in the metal interconnection. However, as semiconductor devices have become smaller, a CD (critical dimension) of the metal interconnection has been reduced, which may make it difficult to form the metal interconnection having a micro-pattern. To fabricate the metal interconnection having a micro-pattern, a damascene process may be used. A plurality of metal interconnections may be fabricated in a multi-layer structure through the damascene process.
However, in a device having a multi-layer metal interconnection structure, parasitic capacitance may exist between a lower metal interconnection and an upper metal interconnection, or between adjacent metal interconnections. This may lower an operational speed of a semiconductor device.
For this reason, an insulating layer, which may include a material having a low dielectric constant (low-k), may surround the metal interconnection and may reduce the parasitic capacitance.
However, to effectively reduce the parasitic capacitance, it may be necessary to use an insulating layer having a dielectric constant (k) corresponding to vacuum permittivity.